Conductive studs are widely used for electrically connecting metal layers of a semiconductor device to underlying conductive members such as diffusion regions, polysilicon layers, or other metal layers. Polysilicon studs are often used as contacts in silicon memory chips, because they can be fabricated with minimal damage to the silicon substrate, thereby minimizing problems associated with junction leakage. (See Bronner et al, VLSI Symp. Proc., 1995, p. 15). The interconnects used to connect these polysilicon studs are often formed by the "damascene" process (see Caanta et al, VMIC Proc., 1991, p. 144). A "damascene" process basically involves forming a trench in an insulating layer such as by etching and filling the trench with a conductive material such as a metal. This is followed by planarization typically achieved by chemical-mechanical polishing (CMP) whereby the metal on the substrate surface outside trench is removed. In contrast, the traditional etch back technique for forming metal wiring (e.g. for interconnects) involves applying a metal layer on a substrate surface, patterning the metal layer by etching (usually reactive ion etching) and filling in the spaces in the metal pattern with a dielectric material. The damascene process offers many advantages compared to the traditional etch back technique, including less erosion of the stud during the metal over-etch, which erosion in an extreme case can cause an open circuit between the metal interconnect and the stud.
Where the damascene process is used to form interconnects over studs, controlling the amount of stud recess during the stud patterning (prior to forming the interconnect trenches) is critical, in part because the damascene interconnect trench etch generally does not affect the stud height significantly. For instance, too little recess results in the studs completely intersecting the interconnect, and a high resistance for the interconnect. (See FIG. 1). On the other hand, too much recess can leave underlying structures such as the gate cap insulator, e.g. silicon nitride, unprotected during the interconnect trench etch, thereby causing high leakage between the interconnects and the gates. See FIG. 2.
From a practical manufacturing standpoint, difficulties exist in controlling the stud recess depth due to buried voids or seams in the polysilicon, which in turn results in very rapid recessing of the stud.